1 the SY100EP15V is a high-speed, low-skew, pecl/ecl 1:4 precision fanout buffer with a 2:1 mux front end in a small 16-pin tssop package. the 2:1 mux input accepts a single-ended pecl/ecl source (clk1) and a differential pecl/ecl/hstl source (clk0). all i/o pins are 100k ep pecl/ecl logic compatible. ac performance is guaranteed over the industrial ?0 c to +85 c temperature range and 3.3v to 5v supply voltage. this device will operate in pecl/lvpecl or ecl/lvecl mode. for clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 225ps produces a toggle frequency as high as 2.5ghz (~400mv pp swing). a v bb output reference pin is available for ac?oupled and single-ended input applications. in addition, a synchronous output enable function is provided. the SY100EP15V is part of micrel? high-speed, precision edge timing and distribution family. for applications that require a different i/o combination, consult micrel's website at www.micrel.com , and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock dividers. features description rev.: a amendment: /0 issue date: may 2002 pin configuration/block diagram SY100EP15V final high-speed 1:4 pecl/ecl fanout buffer 2:1 multiplexer input guaranteed ac parameters over temp/voltage: > 2.5ghz f max (toggle) < 225ps rise/fall times < 25ps within device skew < 425ps propagation delay (clk-to-q) low jitter design: < 1ps (rms) cycle-to-cycle jitter < 1ps (pk-pk) total jitter flexible power supply: 3.3v/5v wide operating temperature range: ?0 c to +85 c v bb reference for ac-coupled or single-ended applications output enable/disable function 100k pecl/ecl compatible logic input accepts pecl/lvpecl/ecl/hstl logic levels available in a 16-pin tssop package 3.3v/5v 2.5ghz pecl/ecl 1:4 fanout buffer with 2:1 input mux 1 q0 /q0 q1 /q1 q2 /q2 q3 /q3 16 vcc /en clk1 vbb /clk0 clk0 sel vee 215 314 413 512 611 710 89 d q 1 0
2 SY100EP15V micrel truth table (1) clk0 clk1 sel /en q lx lll hx l lh xl hll xh hlh xlhl x hhl pin description pin pin number function 1, 2, 3, 4 q0 q3 outputs 0 through 3: 100kep (lv)pecl/(lv)ecl compatible differential outputs. terminate 5, 6, 7, 8 /q0 /q3 with 50 ? to v cc 2v. unused output pairs may be left floating, or pulled-down with a 2k ? resistor to the most negative supply. unused single-ended outputs must have a balanced load. for ac-coupled applications, the output stage emitter follower must have a dc current path to ground. see termination section. 9 vee negative power supply: for pecl/lvpecl applications, connect to gnd. 10 sel 100kep (lv)pecl/(lv)ecl compatible 2:1 mux input select control. see truth table. the select (sel) pin includes an internal 75k ? pull-down resistor. default condition when left floating is low, and clk0 input is selected. 11, 12 clk0, /clk0 differential (lv)pecl/(lv)ecl/hstl compatible input: the inputs include an internal 75k ? pull-down resistor on clk0 and internal 75k ? pull-up and pull-down on /clk0. default condition for clk0 is low when left floating and v cc /2 for /clk0 when left floating. 13 vbb reference output voltage: this reference is typically used to bias the unused inverting input for single-ended input applications, or as the termination point for ac-coupled differential input applications. v bb reference value is approximately v cc 1.3v, and tracks vcc 1:1. maximum sink/source capability for v bb is 0.50ma. for single ended inputs, connect to the unused input through a 50 ? resistor. decouple the v bb pin with a 0.01 f capacitor to v cc . 14 clk1 single-ended (lv)pecl/(lv)ecl compatible input: this pin includes an internal 75k ? pull-down resistor. default condition is low when left floating. 15 /en 100kep (lv)pecl/(lv)ecl compatible input: this synchronous pin controls the output state. see truth table. to ensure proper synchronous operation, adhere to the set-up and hold times, as described in the ac electrical table. when /en pin goes high, q outputs go low, and /q outputs go high on the next falling clock transition. this synchronous operation avoids any chance of generating a runt pulse. 16 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors. note: 1 . = negative edge.
3 SY100EP15V micrel symbol rating value unit v cc v ee power supply voltage 6.0 v v in input voltage (v cc = 0v, v in not more negative than v ee ) 6.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 i out output current continuous 50 ma surge 100 i bb v bb sink/source current (2) 0.5 ma t a operating temperature range 40 to +85 c t store storage temperature range 65 to +150 c ja package thermal resistance still-air (single-layer pcb) 115 (junction-to-ambient) still-air (multi-layer pcb) 75 c/w 500lfpm (multi-layer pcb) 65 jc package thermal resistance 21 c/w (junction-to-case) absolute maximum ratings (1) notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional opera tion is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng con ditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for inputs of same package only. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v cc power supply voltage v (pecl) 4.5 5.0 5.5 4.5 5.0 5.5 4.5 5.0 5.5 (lvpecl) 2.97 3.3 3.63 2.97 3.3 3.63 2.97 3.3 3.63 (ecl) 5.5 5.0 4.5 5.5 5.0 4.5 5.5 5.0 4.5 (lvecl) 3.63 3.3 2.97 3.63 3.3 2.97 3.63 3.3 2.97 i cc power supply current 70 52 72 75 ma i ih input high current 150 150 150 av in = v ih i il input low current clk0, clk1 0.5 0.5 0.5 av in = v il /clk0 150 150 150 av in = v il c in input capacitance (tssop) 1.0 pf dc electrical characteristics (1) note: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.
4 SY100EP15V micrel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1355 1675 1355 1675 1355 1675 mv v cc = 3.3v (single-ended) v ih input high voltage 2075 2420 2075 2420 2075 2420 mv v cc = 3.3v (single-ended) v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v cc = 3.3v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v cc = 3.3v v bb reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cc = 3.3v v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (3) (100kep) lvpecl dc electrical characteristics (1) v cc = 3.0v 10%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output par ameters varies 1:1 with v cc . output load is 50 ? to v cc 2v. 2. v bb varies 1:1 with v cc . 3. the v ihcmr range is referenced to the most positive side of the differential input signal. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 3055 3375 3055 3375 3055 3375 mv v cc = 5v (single-ended) v ih input high voltage 3775 4120 3775 4120 3775 4120 mv v cc = 5v (single-ended) v ol output low voltage 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v cc = 5v v oh output high voltage 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v cc = 5v v bb output voltage reference (2) 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v cc = 5v v ihcmr input high voltage (3) 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (100kep) pecl dc electrical characteristics (1) v cc = 5.0v 10%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output par ameters vary 1:1 with v cc . output load is 50 ? to v cc 2v. 2. v bb varies 1:1 with v cc . 3. the v ihcmr range is referenced to the most positive side of the differential input signal.
5 SY100EP15V micrel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1945 1625 1945 1625 1945 1625 mv (single-ended) v ih input high voltage 1165 880 1165 880 1165 880 mv (single-ended) v ol output low voltage 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv 50 ? to v cc 2v v oh output high voltage 1145 1020 895 1145 1020 895 1145 1020 895 mv 50 ? to v cc 2v v bb output reference voltage 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage v common mode range (2) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 (100kep) lvecl dc electrical characteristics (1) v cc = 0v, v ee = 2.97v to 3.63v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. the v ihcmr range is referenced to the most positive side of the differential input signal. (100k) ecl dc electrical characteristics (1) v cc = 0v, v ee = 4.5v to 5.5v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. the v ihcmr is referenced to the most positive side of the differential input signal. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1945 1625 1945 1625 1945 1625 mv v ih input high voltage 1225 880 1225 880 1225 880 mv v ol output low voltage 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv 50 ? to v cc 2v v oh output high voltage 1145 1020 895 1145 1020 895 1145 1020 895 mv 50 ? to v cc 2v v bb output reference voltage 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage v common mode range (2) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv hstl input dc electrical characteristics v cc = 2.97v to 3.63v, v ee = 0v
6 SY100EP15V micrel product ordering code ordering package operating package code type range marking SY100EP15Vk4i k4-16-1 industrial xep15v SY100EP15Vk4itr* k4-16-1 industrial xep15v *tape and reel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f max (1) maximum frequency 2.5 2.5 2.5 ghz t pd propagationdelay to output pecl/ecl diff. in-to-q 275 425 275 375 425 275 425 ps in (single-ended)-to-q 250 450 250 400 450 250 450 ps sel-to-q 250 450 250 400 450 250 450 ps lvpecl/lvecl diff. in-to-q 275 425 275 375 425 275 425 ps in (single-ended)-to-q 250 450 250 400 450 250 450 ps sel-to-q 250 450 250 400 450 250 450 ps t skew (2) within-device skew (diff.) 25 15 25 25 ps part-to-part skew (diff.) 150 100 150 150 ps t s (3) set-up time /en to clk 100 0 100 0 100 0 ps t h (3) hold time /en to clk 200 50 200 50 200 50 ps t jitter cycle-to-cycle jitter (4) 0.2 1 0.2 1 0.2 1 ps(rms) total jitter (622mhz clock) (5) <1 <1 <1 ps(pk-pk) v id input voltage range 150 800 1200 150 800 1200 150 800 1200 mv t r , t f output rise/fall times 75 225 75 130 225 85 225 ps (20% to 80%) ac electrical characteristics lvpecl: v cc = 2.97v to 3.63v, v ee = 0v; pecl: v cc = 4.5v to 5.5v, v ee = 0v ecl: v cc = 0v, v ee = 4.5v to 5.5v; lvecl: v cc = 0v, v ee = 2.97v to 3.63v notes: 1. f max is defined as the maximum toggle frequency. measured with 750mv input signal, 50% duty cycle, output swing 400mv(diff), all loading with 50 ? to v cc 2v. 2. skew is measured between outputs under identical transitions. 3. set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. for asynch ronous applications, set- up and hold time does not apply. 4. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pair s. t jitter_cc =t n t n+1 where t is the time between rising edges of the output signal. 5. total jitter definition: with an ideal clock input, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value.
7 SY100EP15V micrel termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v figure 1. parallel termination?hevenin equivalent notes: 1. for +2.5v systems: r1 = 250 ? r2 = 62.5 ? 2. for +5.0v systems: r1 = 82 ? r2 = 130 ? z = 50 ? z = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v source destination r b (optional) c1 0.01 f figure 2. three-resistor ??ermination notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? . for +5v systems, r b = 110 ? . 4. c1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3v +3.3v 50 ? z o = 50 ? 0.01 f v bb r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc 2v q /q +3.3v figure 3. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel's differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to v cc , not gnd. 4. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? .
8 SY100EP15V micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2002 micrel incorporated 16 lead tssop (k4-16-1) rev. 01
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